Laugh so hard That even Sorrows Smiles at you ,
Live Life so well That even death loves to see you Alive ,
Fight so hard That even Fate accepts it Defeat.
Live Life so well That even death loves to see you Alive ,
Fight so hard That even Fate accepts it Defeat.
BVLSI Syllabus (KJSCE 2014) and examination scheme
Lecture 01 dated 08-01-2020:
Topics Covered : Introduced students to various Chip makers companies, Showed 4 videos on Evolution of Integrated circuits.
Video 1: Evolution of Intel
Video 2: Zoom into a Micro chip
Video 3: History if Integrated circuits
Video 4: Video Animation of Mark Bohr Gets Small- 22 nm Explained
Module or sub-module covered : Developed motivation for studying MOSFETs
Video 1
Video 2
Video 3
Video 3
Video 4
Lecture 02 dated 09-01-2020:
Topics Covered : Introduction to MOS Capacitor (MOSCAP), Concept of Gate Oxide Capacitance (Cox), and Gate oxide Thinkness (tox), Numerical on Cox, constant's ni, concept of law of mass action, EBD of p type Si
Module or sub-module covered : 1.2
Lecture 03 dated 10-01-2020:
Topics Covered : Concept of Fermi potential, concept of work function difference, Energy Band Diagram (EBD) of isolated MOS Capacitor, EBD of MOSCAP under equilibrium
Module or sub-module covered : 1.2
Topics Covered : Concept of Fermi potential, concept of work function difference, Energy Band Diagram (EBD) of isolated MOS Capacitor, EBD of MOSCAP under equilibrium
Module or sub-module covered : 1.2
bvlsi_lecture_02_03.pdf | |
File Size: | 1495 kb |
File Type: |
bvlsi_mos_capacitor_importance.pdf | |
File Size: | 437 kb |
File Type: |
bvlsi_lecture_02_03_contents_kang.pdf | |
File Size: | 982 kb |
File Type: |
VIDEO 3.1: Energy band diagram of MOS capacitor
Start video from 38 minutes 10 second and watch it till 57 minutes
Start video from 38 minutes 10 second and watch it till 57 minutes
BVLSI Summary for Week 1 ( 6th Jan 2020 - 10th Jan 2020)
Total lectures conducted: 03
Total BVLSI lecture handouts uploaded in website: 03
Lecture 04 dated 15-01-2020:
Topics Covered : Flat band condition in MOS capacitor, MOS Capacitor under external bias: Accumulation, Depletion and Inversion (explanation w.r.t Energy band diagrams)
Module or sub-module covered : 1.2
bvlsi_lecture_04.pdf | |
File Size: | 1264 kb |
File Type: |
bvlsi_moscap_under_external_bias_kang.pdf | |
File Size: | 861 kb |
File Type: |
Lecture 05 dated 16-01-2020:
Topics Covered : Derivation for xd (depletion region depth ) for MOS CAP under depletion condition, QBO expression, Condition for Inversion, MOS Capacitor C-V characteristics for low frequency and high frequency.
Module or sub-module covered : 1.2
bvlsi_lecture_05.pdf | |
File Size: | 2864 kb |
File Type: |
VIDEO lecture on MOS Capacitor under external Bias
ONLINE Simulation of MOS capacitor C-V curve
Website: https://nanohub.org
Steps: Register and login, select from tools, a TCAD Lab, click on Launch button, run a application: MOS Capacitor (classical simulation), select C-V characteristics and click on simulate button to view the C-V curve for a MOS capacitor
MOS Capacitor C-V curve
Lecture 06 dated 17-01-2020:
Topics Covered : Numerical on MOS Capacitor i.e determination of Gate oxide, min gate and flat band capacitance for a MOS Capacitor, Definition of THRESHOLD VOLTAGE for a MOS device, various factors contributing to threshold voltage VTO, expression for VTO
Module or sub-module covered : 1.2
bvlsi_lecture_06.pdf | |
File Size: | 1620 kb |
File Type: |
BVLSI Summary for Week 2 ( 13th Jan 2020 - 17th Jan 2020)
Total lectures conducted: 03
Total BVLSI lecture handouts uploaded in website: 03
Lecture 07 dated 20-01-2020:
Topics Covered : THRESHOLD VOLTAGE for a MOS device for non-zero VSB, Numerical on determining threshold voltage of NMOS and PMOS devices with VSB=0 and VSB non-zero
Module or sub-module covered : 1.2
bvlsi_lecture_07.pdf | |
File Size: | 1810 kb |
File Type: |
Lecture 08 dated 22-01-2020: (2 hours)
Topics Covered 8a (1 hour): THRESHOLD VOLTAGE adjustment for a MOS device, Numerical on THRESHOLD VOLTAGE adjustment of NMOS and PMOS device
Topics Covered 8b (1 hour): Journey from MOS capacitor to MOSFET, concept development for N-channel MOSFET operation with various cases ( total 5 cases)
Module or sub-module covered : 1.2
bvlsi_lecture_8a.pdf | |
File Size: | 1361 kb |
File Type: |
bvlsi_lecture_8b.pdf | |
File Size: | 3433 kb |
File Type: |
BVLSI SOLVED Threshold voltage numerical
bvlsi_threshold_voltage_numerical.pdf | |
File Size: | 875 kb |
File Type: |
VIDEO lecture on MOS capacitor and MOSFET introduction and working
Start video from 13th minute and watch it till the end
Start video from 13th minute and watch it till the end
Lecture 09 dated 23-01-2020: (2 hours) handout uploaded on 29/1/2020
Topics Covered 9a (1 hour): Drain currents ID linear and ID sat derivation for NMOS under Gradual Channel Approximation(GCA), Output characteristics of NMOS
Topics Covered 9b (1 hour): Drain current ID sat derivation under Channel length modulation for NMOS device, numerical on finding the region of operation of MOSFET and finding drain current magnitude
Module or sub-module covered : 1.2
bvlsi_lecture_9a.pdf | |
File Size: | 2959 kb |
File Type: |
bvlsi_lecture_9b.pdf | |
File Size: | 2869 kb |
File Type: |
VIDEO lecture on drain current derivation for an NMOS and its I-V characteristics
VIDEO lecture on drain current derivation for an n-channel E MOSFET and its I-V characteristics (Part 1)
VIDEO lecture on drain current derivation for an n-channel E MOSFET and its I-V characteristics (Part 2)
VIDEO lecture on drain current derivation for an n-channel E MOSFET (Channel Length Modulation)
Start Video and watch it till 14th Minute for above topic on CLM
Start Video and watch it till 14th Minute for above topic on CLM
BVLSI Summary for Week 3 ( 20th Jan 2020 - 24th Jan 2020)
Total lectures conducted: 05
Total BVLSI lecture handouts uploaded in website: 05
Lecture 10 dated 27-01-2020: handout uploaded on 3/2/2020
Topics Covered : Transistor Scaling trends, Scaling Features, Scaling factor, important MOSFET parameters, Types of Scaling Techniques: Constant Field scaling and Constant Voltage scaling.
Module or sub-module covered : 1.3
Lecture 11 dated 29-01-2020: handout uploaded on 3/2/2020
Topics Covered : Comparison between CF and CV scaling (total: 22 points), Advantages of CF and CV scaling, Limitations of CF and CF scaling. Solved two numerical on Scaling
Module or sub-module covered : 1.3
Lecture 11 dated 29-01-2020: handout uploaded on 3/2/2020
Topics Covered : Comparison between CF and CV scaling (total: 22 points), Advantages of CF and CV scaling, Limitations of CF and CF scaling. Solved two numerical on Scaling
Module or sub-module covered : 1.3
bvlsi_lecture_10_11.pdf | |
File Size: | 4281 kb |
File Type: |
Lecture 12 dated 30-01-2020: handout will be uploaded soon
Topics Covered : Limitations of Scaling, Short channel effects, narrow channel effects, hot electron effect, Detailed Short channel effects: A) Velocity saturation, B) Mobility degradation, C) Charge Sharing d) DIBL e) Punch through and f) Sub-Threshold conduction
Module or sub-module covered : 1.3
VIDEO lecture on Velocity Saturation for small geometry MOSFETs
Watch it from start and watch it till 19 minutes
VIDEO lecture on Drain Induced Barrier Lowering for small geometry MOSFETs
VIDEO lecture on Sub threshold current (Ioff current) for small geometry MOSFETs
VIDEO lecture on Substrate and Gate Leakage for small geometry MOSFETs
(Need for Hi-k dielectric material is also discussed in the video
(Need for Hi-k dielectric material is also discussed in the video
VIDEO lecture on PMOS Transistor (Kindly refer this once, as PMOS is compliment of NMOS, all current ID equations derived for NMOS are valid for PMOS, only polarity difference is there... Watch Out...)
Lecture 13 dated 31-01-2020: (2 hours) handout uploaded on 3/2/2020
Topics Covered 13a (1 hour): MOSFET Capacitance, Top view and cross section view of N-channel E-MOSFET, classification of MOSFET capacitance, Gate overlap capacitance: It's origin & determination , Gate parasitic capacitance: It's origin & determination
Topics Covered 13b (1 hour): Junction capacitance, determining expression for Cj(V), large signal equivalent capacitance Cjeqvt (V), Sidewall junction capacitance estimation
Module or sub-module covered : 1.2
bvlsi_lecture_13a.pdf | |
File Size: | 1701 kb |
File Type: |
bvlsi_lecture_13b.pdf | |
File Size: | 2501 kb |
File Type: |
bvlsi_mosfet_capacitance_numerical_02.pdf | |
File Size: | 486 kb |
File Type: |
bvlsi_mosfet_capacitance_numerical_03.pdf | |
File Size: | 837 kb |
File Type: |
BVLSI Summary for Week 4 ( 27th Jan 2020 - 31st Jan 2020)
Total lectures conducted: 05
Total BVLSI lecture handouts uploaded in website: 05
Lecture 14 dated 06-02-2020: (2 hours) handout uploaded on 9/2/2020
Topics Covered 14a (1 hour): Basic inverter DC (Static Characteristic) or VTC curve, Inverter expectations, VTC curve detailed analysis and important information on 5 critical parameters ( VOL, VIH, VIL, VOL, VTH), Propagation of digital signal under the influence of noise (Effect of noise on circuit reliability) , Noise margins ( NML, NMH) definitions, Justification for taking slope of (dVout/dVin = -1) for estimation of VIL and VIH on VTC curve.
Topics Covered 14b (1 hour): MOS inverter parameters ( Static and dynamic) Overview, Analysis and working of Resistive load NMOS inverter, derivation for VOL, VOH, VIH, VTH and VIL for Resistive load NMOS inverter.
Module or sub-module covered : 2.1
Lecture 14 dated 06-02-2020: (2 hours) handout uploaded on 9/2/2020
Topics Covered 14a (1 hour): Basic inverter DC (Static Characteristic) or VTC curve, Inverter expectations, VTC curve detailed analysis and important information on 5 critical parameters ( VOL, VIH, VIL, VOL, VTH), Propagation of digital signal under the influence of noise (Effect of noise on circuit reliability) , Noise margins ( NML, NMH) definitions, Justification for taking slope of (dVout/dVin = -1) for estimation of VIL and VIH on VTC curve.
Topics Covered 14b (1 hour): MOS inverter parameters ( Static and dynamic) Overview, Analysis and working of Resistive load NMOS inverter, derivation for VOL, VOH, VIH, VTH and VIL for Resistive load NMOS inverter.
Module or sub-module covered : 2.1
bvlsi_lecture_14a.pdf | |
File Size: | 3907 kb |
File Type: |
bvlsi_lecture_14b.pdf | |
File Size: | 2068 kb |
File Type: |
BVLSI Summary for Week 5 ( 3rd Feb 2020 - 7th Feb 2020)
Total lectures conducted: 02
Total BVLSI lecture handouts uploaded in website: 02
Lecture 15 dated 11-02-2020: handout uploaded on 16/2/2020
Topics Covered: DC Static Power Dissipation in Resistive load nMOS inverter , numerical on Noise margins estimation for a restive load nMOS inverter, Showed LT Spice circuit ( same as numerical) simulation LIVE in class and estimated noise margin levels from VTC curve, Impact of knRL term on VTC curve, Limitation in a resistive load nMOS inverter
Module or sub-module covered : 2.1
Topics Covered: DC Static Power Dissipation in Resistive load nMOS inverter , numerical on Noise margins estimation for a restive load nMOS inverter, Showed LT Spice circuit ( same as numerical) simulation LIVE in class and estimated noise margin levels from VTC curve, Impact of knRL term on VTC curve, Limitation in a resistive load nMOS inverter
Module or sub-module covered : 2.1
bvlsi_lecture_15.pdf | |
File Size: | 1257 kb |
File Type: |
Lecture 16 dated 12-02-2020: handout uploaded on 16/2/2020
Topics Covered: Design of Resistive load nMOS inverter, CMOS inverter circuit and description, operating conditions for NMOS and PMOS as per CMOS circuit conditions.
Module or sub-module covered : 2.1
bvlsi_lecture_16.pdf | |
File Size: | 742 kb |
File Type: |
Lecture 17 dated 13-02-2020: (2 hours)
Topics Covered 17a (1 hour): Detailed working(with numbers) of CMOS inverter (Region A to E) w.r.t VTC curve
Topics Covered 17b (1 hour): CMOS inverter parameters derivation: VOL, VOH, VIH, VTH and VIL, Numerical based on asymmetric CMOS inverter noise margin estimation, Showed LT Spice circuit ( same as numerical) simulation LIVE in class and estimated noise margin levels from VTC curve, Impact of inverter ratio kr on VTC curve
Module or sub-module covered : 2.1
Lecture 17 dated 13-02-2020: (2 hours)
Topics Covered 17a (1 hour): Detailed working(with numbers) of CMOS inverter (Region A to E) w.r.t VTC curve
Topics Covered 17b (1 hour): CMOS inverter parameters derivation: VOL, VOH, VIH, VTH and VIL, Numerical based on asymmetric CMOS inverter noise margin estimation, Showed LT Spice circuit ( same as numerical) simulation LIVE in class and estimated noise margin levels from VTC curve, Impact of inverter ratio kr on VTC curve
Module or sub-module covered : 2.1
BVLSI Summary for Week 6 ( 10th Feb 2020 - 14th Feb 2020)
Total lectures conducted: 04
Total BVLSI lecture handouts uploaded in website: 02
Lecture 18 dated 26-02-2020:
Topics Covered: Static Vs Dynamic logic styles, Computational logic Vs Sequential logic, Concept of Fan-in and Fan-out, Static logic definition & types, General Structure of Static CMOS logic, Method to realize a logic expression using Static CMOS logic( Pull-down and Pull-up network) Realization of 2 input NAND gate using Static CMOS logic, Realization of 2 input NOR gate using Static CMOS logic, Realization of 4 inputs logic expression using Static CMOS logic, Realization of 8 inputs logic expression using Static CMOS logic ( given as Home assignment)
Simulations Covered: LT Spice simulation ( showed live in class) of 2 input NAND Gate using Static CMOS Logic
Module or sub-module covered : 3.1
Topics Covered: Static Vs Dynamic logic styles, Computational logic Vs Sequential logic, Concept of Fan-in and Fan-out, Static logic definition & types, General Structure of Static CMOS logic, Method to realize a logic expression using Static CMOS logic( Pull-down and Pull-up network) Realization of 2 input NAND gate using Static CMOS logic, Realization of 2 input NOR gate using Static CMOS logic, Realization of 4 inputs logic expression using Static CMOS logic, Realization of 8 inputs logic expression using Static CMOS logic ( given as Home assignment)
Simulations Covered: LT Spice simulation ( showed live in class) of 2 input NAND Gate using Static CMOS Logic
Module or sub-module covered : 3.1
LT Spice simulation: 2 input NAND Gate using Static CMOS Logic
Lecture A dated 26-02-2020: (30 minutes)
(Lecture series on every Wednesday and Thursday after regular BVLSI lecture) AIM: to cover Module 2 syllabus
Topics Covered: Symmetric CMOS inverter conditions, Numerical on Symmetric CMOS inverter to estimate noise margin levels
Module or sub-module covered : 2.1
Lecture A dated 26-02-2020: (30 minutes)
(Lecture series on every Wednesday and Thursday after regular BVLSI lecture) AIM: to cover Module 2 syllabus
Topics Covered: Symmetric CMOS inverter conditions, Numerical on Symmetric CMOS inverter to estimate noise margin levels
Module or sub-module covered : 2.1
Lecture 19 dated 27-02-2020:
Topics Covered: Realization of 2 input XOR gate using Static CMOS logic, Realization of 2 input XNOR gate using Static CMOS logic, Merits and Demerits of Static CMOS Logic Design style, Ratioed logic: concept & general structure, Pseudo NMOS logic: concept & structure, Realization of 2 input NAND gate using Pseudo NMOS logic, Realization of 4 input NOR gate using Pseudo NMOS logic, Properties of Pseudo NMOS logic, Impact of Sizing of PMOS transistor on VTC curve of Pseudo NMOS logic, Merits and Demerits of Pseudo NMOS Logic Design style
Simulations Covered: LT Spice simulation ( showed live in class) of
1. Impact of Sizing ( W/L ratios ) of PMOS transistor on VTC curve of Pseudo NMOS logic
2. Two input NAND gate using Pseudo NMOS Logic
3. Comparison of Stronger Pull-up and Stronger Pull-down network in a Two input NAND gate using Pseudo NMOS Logic
Module or sub-module covered : 3.1
LT Spice simulation: Two input NAND gate using Pseudo NMOS Logic
LT Spice simulation: Comparison of Stronger Pull-up and Stronger Pull-down network in a Two input NAND gate using Pseudo NMOS Logic
LT Spice simulation: Impact of Sizing ( W/L ratios ) of PMOS transistor on VTC curve of Pseudo NMOS logic
Lecture B dated 27-02-2020: (45 minutes)
(Lecture series on every Wednesday and Thursday after regular BVLSI lecture) AIM: to cover Module 2 syllabus
Topics Covered: Derivation for symmetric CMOS inverter conditions, Numerical on Symmetric CMOS inverter to estimate noise margin levels, Impact of inverter ratio (Kr) on VTC curve of CMOS inverter
Module or sub-module covered : 2.1
Lecture 20 dated 28-02-2020:
Topics Covered: Pass transistor Logic (PTL), Realization of 2 input AND gate using N pass transistor logic, Realization of 2 input NAND gate using N pass transistor logic, Realization of 2 input XOR gate using N pass transistor logic, Realization of 2 input XNOR gate using N pass transistor logic, Realization of 3 input logic expression gate using N pass transistor logic, Realization of 2 input XOR gate using P pass transistor logic, Concept of Pass transistors, NMOS as N Pass transistor ( NMOS Charging: Not a Good transmitter of Logic '1', NMOS Discharging: Good Transmitter of Logic '0'), PMOS as P Pass transistor ( PMOS Charging: Good transmitter of Logic '1', PMOS Discharging: Not a Good Transmitter of Logic '0')
Simulations Covered: LT Spice simulation ( showed live in class) of
1. NMOS as N Pass transistor (NMOS Charging: Not a Good transmitter of Logic '1', NMOS Discharging: Good Transmitter of Logic '0')
2. PMOS as P Pass transistor (PMOS Charging: Good transmitter of Logic '1', PMOS Discharging: Not a Good Transmitter of Logic '0')
3. Reverse CMOS inverter (NMOS as pull-up device and PMOS as pull-down device)
Module or sub-module covered : 3.1
LT Spice simulation: NMOS as N Pass transistor (NMOS Charging: Not a Good transmitter of Logic '1', NMOS Discharging: Good Transmitter of Logic '0')
LT Spice simulation: PMOS as P Pass transistor (PMOS Charging: Good transmitter of Logic '1', PMOS Discharging: Not a Good Transmitter of Logic '0')
LT Spice simulation: PMOS as P Pass transistor (PMOS Charging: Good transmitter of Logic '1', PMOS Discharging: Not a Good Transmitter of Logic '0')
LT Spice simulation: Reverse CMOS inverter (NMOS as pull-up device and PMOS as pull-down device)
VIDEO lecture on NMOS & PMOS: Charging and Discharging
Watch it from 6 minutes onward's and watch it till the end
BVLSI Summary for Week 7 ( 24th Feb 2020 - 28th Feb 2020)
Total lectures conducted: 05
Total BVLSI lecture handouts uploaded in website: 00
Total LT Spice Simulation Pics uploaded in website: 18
Total Video lecture uploaded in website: 01
Lecture 21 dated 04-03-2020:
Topics Covered: Realization of 2 input X NOR gate using PMOS pass transistor logic, Complementary Pass Transistor logic(CPL), Realization of 2 input OR-NOR gates using CPL logic, Realization of 2 input AND-NAND gates using CPL logic, Realization of 2 input XOR-X NOR gates using CPL logic, Limitations of Pass transistor logic.
Module or sub-module covered : 3.1
Lecture C dated 04-03-2020: (60 minutes)
(Lecture series on every Wednesday and Thursday after regular BVLSI lecture)
Topics Covered: Transmission gate(TG) : Concept, working & symbol of TG, Realization of 2 input OR gate using TG logic, Realization of 2 input NAND gate using TG logic, Realization of 2 input NOR gate using TG logic, Realization of 2 input XOR gate using TG logic, Realization of 2 input
X NOR gate using TG logic, Realization of Boolean expression using TG logic
Simulations Covered: LT Spice simulation ( showed live in class) of
1. Circuit simulation of XOR gate using N Pass transistor logic
2. Circuit simulation of XOR gate using transmission gate logic
Module or sub-module covered : 3.1
,
Lecture 22 dated 05-03-2020:
Topics Covered: Dynamic CMOS logic: Basic Concept, basic general structure, Pre-charge and Evaluation phases with example, Realization of Boolean expression using Dynamic CMOS logic, Properties of Dynamic CMOS Logic, Realization of 4 input NAND gate using Dynamic CMOS logic, Signal integrity issues in Dynamic CMOS logic
Module or sub-module covered : 3.1
Lecture 22 dated 05-03-2020:
Topics Covered: Dynamic CMOS logic: Basic Concept, basic general structure, Pre-charge and Evaluation phases with example, Realization of Boolean expression using Dynamic CMOS logic, Properties of Dynamic CMOS Logic, Realization of 4 input NAND gate using Dynamic CMOS logic, Signal integrity issues in Dynamic CMOS logic
Module or sub-module covered : 3.1
Lecture D dated 05-03-2020: (30 minutes)
(Lecture series on every Wednesday and Thursday after regular BVLSI lecture) AIM: to cover Module 2 syllabus
Topics Covered: Switching/Dynamic characteristics of CMOS inverter, Delay time definitions: High to low & low to high propagation delay, rise time and fall time.
Module or sub-module covered : 2.1
Lecture 23 dated 06-03-2020:
Topics Covered: Realization of Boolean expression using Dynamic CMOS logic ( revision of Pre=-charge & evaluation phase) , Dynamic CMOS logic limitations: 1) Charge Leakage (Concept + explanation) 2) Capacitive coupling (Concept + explanation) 3) Clock feed-through (Concept + explanation) & 4) Charge sharing( only intro)
Module or sub-module covered : 3.1
BVLSI Summary for Week 8 ( 2nd March 2020 - 6th March 2020)
Total lectures conducted: 05
Total BVLSI lecture handouts uploaded in website: 00
Total LT Spice Simulation Pics uploaded in website: 00
Total Video lecture uploaded in website: 00
Lecture 24 dated 11-03-2020:
Topics Covered: Charge sharing (concept with example), Cascading/Race problem in Dynamic CMOS logic, Dynamic CMOS logic limitations (review), Domino CMOS logic: (General structure + working with specific scenario + Properties)
Module or sub-module covered : 3.1
Lecture 25 dated 12-03-2020: (120 minutes)
Topics Covered: Circuit to compensate charge leakage & charge sharing in Domino CMOS logic: Keeper MOS/ Bleeder transistor in Domino CMOS logic, Cascading Domino CMOS Logic (working with specific scenario), Implementation of complex Boolean expression using i) Static CMOS logic ii) Domino CMOS logic, Concept of MODL (Multiple output Domino logic), Implementation of complex Boolean expressions (two) using MODL logic, Implementation of complex Boolean expressions (three) using MODL logic, NORA ( NP logic) CMOS logic: (General structure + working with specific scenario + Advantages+ Limitations)
Module or sub-module covered : 3.1
Lecture 26 dated 13-03-2020:
Topics Covered: Circuit to compensate charge leakage & charge sharing in NORA CMOS logic: Zipper CMOS logic, Zipper CMOS logic: (General structure + working with specific scenario + Advantages+ Limitations), Clocked CMOS Logic (General structure + working with specific scenario + Advantages+ Limitations),Implementation of 3 input NAND gate using Clocked CMOS Logic, Implementation of complex Boolean expressions using Clocked CMOS Logic
Module or sub-module covered : 3.1
BVLSI Summary for Week 9 ( 8th March 2020 - 13th March 2020)
Total lectures conducted: 04
Total BVLSI lecture handouts uploaded in website: 00
Total LT Spice Simulation Pics uploaded in website: 00
Total Video lecture uploaded in website: 00
BVLSI Test 1 solution
bvlsi_test_1_solution.pdf | |
File Size: | 1559 kb |
File Type: |
MODULE 3.2: BVLSI Online Interactive session (Zoom Cloud Meeting)
In view of unprecedented circumstances ( i.e Pandemic outbreak), BVLSI classroom lectures are suspended. In light of the current situation, an online BVLSI interactive session is arranged for your reference.
I hope this helps until the college resumes.
Details of online BVLSI interactive session conducted on 28th March 2020 are given below:
INDERJIT SINGH DHANJAL is inviting you to a scheduled Zoom meeting.
Topic: INDERJIT SINGH DHANJAL's (BVLSI session 01)
Time: Mar 28, 2020 01:30 PM India
Join Zoom Meeting ( via mobile or Laptop/Desktop)
https://zoom.us/j/8312874873
Meeting ID: 831 287 4873
Topics discussed during these sessions:
BVLSI Session 01
1. Multiplexer circuit realization using Pass transistor & Transmission gate
Detailed coverage 2:1 Mux implementation using Pass transistor & Transmission gate
Concept Over-view of 4:1 Mux realization using Pass transistor & Transmission gate
BVLSI Session 02
2. Decoder circuit realization using Pass transistor & Transmission gate
Detailed coverage of 1:2 Decoder using Pass transistor & Transmission gate
Concept Over-view of 2 line to 4 line decoder circuit realization using Pass transistor & Transmission gate
YouTube VIDEO's are also complied; for those who have missed this interactive session...
Our Motto: Learning never stops
BVLSI Online Session 03 dated 31st March 2020
Details of online BVLSI interactive session conducted on 31st March 2020 are given below:
INDERJIT SINGH DHANJAL is inviting you to a scheduled Zoom meeting.
Topic: INDERJIT SINGH DHANJAL's Zoom Meeting
Time: Mar 31, 2020 05:30 PM India
Join Zoom Meeting
https://zoom.us/j/8312874873
Meeting ID: 831 287 4873
Topics discussed during BVLSI Session 03:
1. Sequential Logic
2. Types of Sequential circuits
3. Difference between Latch and flip-flop
4. CMOS Bistable circuit ( LT Spice Simulation inclusive)
5. CMOS SR Latch(NOR) Based ( LT Spice Simulation inclusive)
YouTube VIDEO is also complied; for those who have missed this interactive session...
Kindly study the topics covered in BVLSI session 03, before the next BVLSI session
BVLSI Online Session 04 dated 1st April 2020
Details of online BVLSI interactive session conducted on 1st April 2020 is given below:
Topic: INDERJIT SINGH DHANJAL's BVLSI Session 04
Time: Apr 1, 2020 12:15 PM India
Topics discussed:
Session (A)
1. CMOS SR Latch NAND Based circuit (LT Spice Simulation inclusive)
2. Clocked SR Latch NOR Based circuit (AOI gates) (LT Spice Simulation inclusive)
3. Clocked SR Latch NAND Based (Active low inputs) circuit (OAI gates) (LT Spice Simulation inclusive)
5 minute-break interval
Session (B)
4. Clocked SR Latch NAND Based (Active high inputs) circuit
5. Clocked JK latch NOR Based circuit (AOI gates) (LT Spice Simulation inclusive)
6. Clocked JK Latch NAND Based circuit
The above session was be split into 2 sessions with a 5-minute break interval.
YouTube VIDEO's are also complied; for those who have missed this interactive session...
BVLSI Online Session 05 dated 4th April 2020
Details of online BVLSI interactive session conducted on 4th April 2020 is given below:
Topic: INDERJIT SINGH DHANJAL's BVLSI Session 05
Time: Apr 4, 2020 01:45 PM India
Meeting ID: 831 287 4873
Topics discussed:
The session covered the transistor level implementation using Static CMOS logic of :
1. Clocked JK latch (NAND based) circuit implementation with detailed working cases
2. Clocked JK latch (NAND based) with active low preset and clear implementation
3. Master-Slave JK Flip-Flop (NOR based- AOI logic) circuit implementation
4. Master-Slave JK Flip-Flop (NAND based) circuit implementation
YouTube VIDEO's are also complied; for those who have missed this interactive session...
BVLSI online session 5 video link: https://youtu.be/D5f1QsMlNME
YouTube videos for Earlier BVLSI sessions:
BVLSI online session 4 A video link: https://youtu.be/oPSKmARJ2MY
BVLSI online session 4 B video link: https://youtu.be/Y7MnSRiGoc4
BVLSI online session 3 video link: https://youtu.be/v2oyqgvuTDI
BVLSI online session 2 video link: https://youtu.be/xmAuSS3qVJg
BVLSI online session 1 video link: https://youtu.be/624TK-apuUQ
BVLSI Online Session 06 dated 5th April 2020
Details of BVLSI online interactive session conducted on April 5, 2020
Topic: INDERJIT SINGH DHANJAL's BVLSI Session 06
Time: Apr 5, 2020 04:30 PM India
Meeting ID: 831 287 4873
Topics discussed are below:
BVLSI Session 6 A:
Transistor level implementation of:
1. D Latch using Static CMOS logic (LT Spice simulation inclusive)
2. Clocked D latch using Static CMOS logic (LT Spice simulation inclusive)
2 minutes break interval
BVLSI Session 6 B:
Transistor level implementation of:
1. Positive Level Triggered D Latch using CMOS Transmission gate logic (LT Spice simulation inclusive)
2. Negative Level Triggered D Latch using CMOS Transmission gate logic (LT Spice simulation inclusive)
3. Positive Level Triggered D Latch using Pass Transistor logic (LT Spice simulation inclusive)
4. Negative Level Triggered D Latch using Pass Transistor logic (LT Spice simulation inclusive)
5 minutes break interval
BVLSI Session 6 C:
Transistor level implementation of:
1. Negative Edge Triggered D flip-flop using CMOS Transmission gate logic (LT Spice simulation inclusive)
2. Dynamic D flip-flop using Pass Transistor Logic (LT Spice simulation inclusive)
3. Dynamic D flip-flop using CMOS Transmission gate Logic (LT Spice simulation inclusive)
4. Dynamic positive Edge Triggered D flip-flop using Pass Transistor Logic (LT Spice simulation inclusive)
5. Dynamic positive Edge Triggered D flip-flop using CMOS Transmission gate logic
5 minutes break interval
BVLSI Session 6 D:
Transistor level implementation of:
1. D flip-flop using C2MOS logic (LT Spice simulation inclusive)
2. Master-Slave positive Edge Triggered D flip-flop using C2MOS logic (LT Spice simulation inclusive)
YouTube VIDEO's are also complied; for those who have missed this interactive session...
BVLSI online session 6 A video link: https://youtu.be/USDicKs0vKQ
BVLSI online session 6 B video link: https://youtu.be/upgoE-lkilU
BVLSI online session 6 C video link: https://youtu.be/GuYrSJLD57w
BVLSI online session 6 D video link: https://youtu.be/oOgEtQfoajs
YouTube videos for Earlier BVLSI sessions:
BVLSI online session 5 video link: https://youtu.be/D5f1QsMlNME
BVLSI online session 4 A video link: https://youtu.be/oPSKmARJ2MY
BVLSI online session 4 B video link: https://youtu.be/Y7MnSRiGoc4
BVLSI online session 3 video link: https://youtu.be/v2oyqgvuTDI
BVLSI online session 2 video link: https://youtu.be/xmAuSS3qVJg
BVLSI online session 1 video link: https://youtu.be/624TK-apuUQ
BVLSI Online Session 06 dated 5th April 2020
Details of BVLSI online interactive session conducted on April 5, 2020
Topic: INDERJIT SINGH DHANJAL's BVLSI Session 06
Time: Apr 5, 2020 04:30 PM India
Meeting ID: 831 287 4873
Topics discussed are below:
BVLSI Session 6 A:
Transistor level implementation of:
1. D Latch using Static CMOS logic (LT Spice simulation inclusive)
2. Clocked D latch using Static CMOS logic (LT Spice simulation inclusive)
2 minutes break interval
BVLSI Session 6 B:
Transistor level implementation of:
1. Positive Level Triggered D Latch using CMOS Transmission gate logic (LT Spice simulation inclusive)
2. Negative Level Triggered D Latch using CMOS Transmission gate logic (LT Spice simulation inclusive)
3. Positive Level Triggered D Latch using Pass Transistor logic (LT Spice simulation inclusive)
4. Negative Level Triggered D Latch using Pass Transistor logic (LT Spice simulation inclusive)
5 minutes break interval
BVLSI Session 6 C:
Transistor level implementation of:
1. Negative Edge Triggered D flip-flop using CMOS Transmission gate logic (LT Spice simulation inclusive)
2. Dynamic D flip-flop using Pass Transistor Logic (LT Spice simulation inclusive)
3. Dynamic D flip-flop using CMOS Transmission gate Logic (LT Spice simulation inclusive)
4. Dynamic positive Edge Triggered D flip-flop using Pass Transistor Logic (LT Spice simulation inclusive)
5. Dynamic positive Edge Triggered D flip-flop using CMOS Transmission gate logic
5 minutes break interval
BVLSI Session 6 D:
Transistor level implementation of:
1. D flip-flop using C2MOS logic (LT Spice simulation inclusive)
2. Master-Slave positive Edge Triggered D flip-flop using C2MOS logic (LT Spice simulation inclusive)
YouTube VIDEO's are also complied; for those who have missed this interactive session...
BVLSI online session 6 A video link: https://youtu.be/USDicKs0vKQ
BVLSI online session 6 B video link: https://youtu.be/upgoE-lkilU
BVLSI online session 6 C video link: https://youtu.be/GuYrSJLD57w
BVLSI online session 6 D video link: https://youtu.be/oOgEtQfoajs
YouTube videos for Earlier BVLSI sessions:
BVLSI online session 5 video link: https://youtu.be/D5f1QsMlNME
BVLSI online session 4 A video link: https://youtu.be/oPSKmARJ2MY
BVLSI online session 4 B video link: https://youtu.be/Y7MnSRiGoc4
BVLSI online session 3 video link: https://youtu.be/v2oyqgvuTDI
BVLSI online session 2 video link: https://youtu.be/xmAuSS3qVJg
BVLSI online session 1 video link: https://youtu.be/624TK-apuUQ
BVLSI online recorded session on April 8, 2020
Details of BVLSI online recorded session on April 8, 2020
Topics discussed:
BVLSI Recorded Session 1 dated 8/4/2020:
Transistor level implementation of:
1:2 decoder (NOR based) circuit using Static CMOS Logic with LT Spice simulation (Schematic + Waveforms)
BVLSI Recorded Session 2 dated 8/4/2020:
Transistor level implementation of:
1:2 decoder (NAND based) circuit using Static CMOS Logic with LT Spice simulation (Schematic + Waveforms)
YouTube VIDEO's complied for this recorded session;
BVLSI online recorded session 1 dated 8/4/2020: https://youtu.be/99lAj9w5jX8
BVLSI online recorded session 2 dated 8/4/2020: https://youtu.be/74MFLB3tqCQ
YouTube videos for Earlier BVLSI sessions:
BVLSI online session 6 A video link: https://youtu.be/USDicKs0vKQ
BVLSI online session 6 B video link: https://youtu.be/upgoE-lkilU
BVLSI online session 6 C video link: https://youtu.be/GuYrSJLD57w
BVLSI online session 6 D video link: https://youtu.be/oOgEtQfoajs
BVLSI online session 5 video link: https://youtu.be/D5f1QsMlNME
BVLSI online session 4 A video link: https://youtu.be/oPSKmARJ2MY
BVLSI online session 4 B video link: https://youtu.be/Y7MnSRiGoc4
BVLSI online session 3 video link: https://youtu.be/v2oyqgvuTDI
BVLSI online session 2 video link: https://youtu.be/xmAuSS3qVJg
BVLSI online session 1 video link: https://youtu.be/624TK-apuUQ
BVLSI supplementary slides
bvlsi_sequential_circuits.pdf | |
File Size: | 3553 kb |
File Type: |
bvlsi_module_4.pdf | |
File Size: | 1731 kb |
File Type: |
bvlsi_nand_nor_rom_array_kang.pdf | |
File Size: | 1707 kb |
File Type: |
BVLSI online recorded session on April 11, 2020
Details of BVLSI online recorded session on April 11, 2020
Topics discussed:
BVLSI Recorded Session 1 dated 11/4/2020:
Transistor level implementation of:
Half adder circuit using Static CMOS Logic with LT Spice simulation (Schematic + Waveforms)
BVLSI Recorded Session 2 dated 11/4/2020:
Transistor level implementation of:
Full adder circuit using Static CMOS Logic with LT Spice simulation (Schematic + Waveforms)
BVLSI Recorded Session 3 dated 11/4/2020:
Transistor level implementation of:
Full adder circuit (utilizing inversion property) using Static CMOS Logic with LT Spice simulation (Schematic + Waveforms)
BVLSI Recorded Session 4 dated 11/4/2020:
Transistor level implementation of:
Full adder circuit using Complementary Pass Transistor logic with LT Spice simulation (Schematic + Waveforms)
BVLSI Recorded Session 5 dated 11/4/2020:
Transistor level implementation of:
Full adder circuit using Mirror logic with LT Spice simulation (Schematic + Waveforms)
YouTube VIDEO's complied for this recorded session;
BVLSI online recorded session 1 dated 11/4/2020: https://youtu.be/GrKe5-RkL2M
BVLSI online recorded session 2 dated 11/4/2020: https://youtu.be/GJVcVidkU-A
BVLSI online recorded session 3 dated 11/4/2020: https://youtu.be/bKBns1ErM8E
BVLSI online recorded session 4 dated 11/4/2020: https://youtu.be/6cl1uOo9TOw
BVLSI online recorded session 5 dated 11/4/2020: https://youtu.be/BflzLRjsECM
YouTube videos for Earlier BVLSI sessions:
BVLSI online recorded session 1 dated 8/4/2020: https://youtu.be/99lAj9w5jX8
BVLSI online recorded session 2 dated 8/4/2020: https://youtu.be/74MFLB3tqCQ
BVLSI online session 6 A video link: https://youtu.be/USDicKs0vKQ
BVLSI online session 6 B video link: https://youtu.be/upgoE-lkilU
BVLSI online session 6 C video link: https://youtu.be/GuYrSJLD57w
BVLSI online session 6 D video link: https://youtu.be/oOgEtQfoajs
BVLSI online session 5 video link: https://youtu.be/D5f1QsMlNME
BVLSI online session 4 A video link: https://youtu.be/oPSKmARJ2MY
BVLSI online session 4 B video link: https://youtu.be/Y7MnSRiGoc4
BVLSI online session 3 video link: https://youtu.be/v2oyqgvuTDI
BVLSI online session 2 video link: https://youtu.be/xmAuSS3qVJg
BVLSI online session 1 video link: https://youtu.be/624TK-apuUQ
BVLSI online recorded session on April 19, 2020 & May 4,2020 & May 5,2020 & May 6,2020
Details of BVLSI online recorded session on April 19, 2020 & May 4,2020 & May 5,2020 & May 6,2020
Topics discussed:
BVLSI Recorded Session 1 dated 19/4/2020:
1 Bit Full adder circuit using Transmission Gates with LT Spice simulation (Schematic + Waveform's)
BVLSI Online Recorded Session dated 4/5/2020:
Ripple Carry Adder (Concept+ Equations + 4 bit RCA block diagram+Limitations), Carry Look Ahead (CLA) Adder (Concept + CLA Equations + 4 bit CLA block diagram+Strengths+ Limitations)
BVLSI Online Recorded Session 1 dated 5/5/2020:
Transistor level implementation of 4 Bit Carry Look Ahead Adder using Static CMOS Logic (Design on paper consisting of 178 Transistors) + Design implemented in LT Spice with simulated waveforms verifying addition of two 4 bit binary number with 10 different cases)
(Important Lecture)
BVLSI Online Recorded Session 2 dated 5/5/2020:
Transistor level implementation of 4 Bit Carry Look Ahead Adder using Pseudo NMOS Logic
BVLSI Online Recorded Session 3 dated 5/5/2020:
Transistor level implementation of 4 Bit Carry Look Ahead Adder using Dynamic CMOS Logic
BVLSI Online Recorded Session 4 dated 5/5/2020:
Transistor level implementation of 4 Bit Carry Look Ahead Adder using Mirror CMOS Logic (Design on paper consisting of 162 Transistors) + Design implemented in LT Spice with simulated waveforms verifying addition of two 4 bit binary number with 10 different cases)
BVLSI Online Recorded Session 5 dated 5/5/2020:
Transistor level implementation of 4 Bit Carry Look Ahead Adder using Domino CMOS Logic (with MODL Logic for 4 Bit Carry Circuit)
BVLSI Online Recorded Session dated 6/5/2020:
Concept of Manchester Carry Generation, Modified Truth table of 1 Bit Full adder with Carry Kill term, 1 Bit Manchester Carry circuit implementation using Static CMOS logic (Design on Paper + LT Spice simulation), 1 Bit Manchester Carry circuit implementation using Static CMOS with TG (Design on Paper + LT Spice simulation), 1 bit Manchester Carry circuit implementation using Dynamic CMOS circuit (Design on Paper + LT Spice simulation), 4 bit Dynamic Manchester Carry Circuit
YouTube VIDEO's complied for this recorded session;
BVLSI Online Recorded Session dated 4/5/2020: https://youtu.be/yy1PgD4SzJI
BVLSI Online Recorded Session 1 dated 5/5/2020: https://youtu.be/WItAXzrfPrE
BVLSI Online Recorded Session 2 dated 5/5/2020: https://youtu.be/YNiHvMGbVc0
BVLSI Online Recorded Session 3 dated 5/5/2020: https://youtu.be/uOH9DEFabvA
BVLSI Online Recorded Session 4 dated 5/5/2020: https://youtu.be/7yddmCV1kVo
BVLSI Online Recorded Session 5 dated 5/5/2020: https://youtu.be/ygHoPN5HwMY
BVLSI Online Recorded Session dated 6/5/2020: https://youtu.be/ICp1_BVyuAs
Students are encouraged to ask if any doubts related to the video if any in the comment section of Video
Earlier YouTube video links:
BVLSI online recorded session dated 19/4/2020: https://youtu.be/zw78hvpVsWI
BVLSI online recorded session 1 dated 11/4/2020: https://youtu.be/GrKe5-RkL2M
BVLSI online recorded session 2 dated 11/4/2020: https://youtu.be/GJVcVidkU-A
BVLSI online recorded session 3 dated 11/4/2020: https://youtu.be/bKBns1ErM8E
BVLSI online recorded session 4 dated 11/4/2020: https://youtu.be/6cl1uOo9TOw
BVLSI online recorded session 5 dated 11/4/2020: https://youtu.be/BflzLRjsECM
BVLSI online recorded session 1 dated 8/4/2020: https://youtu.be/99lAj9w5jX8
BVLSI online recorded session 2 dated 8/4/2020: https://youtu.be/74MFLB3tqCQ
BVLSI online session 6 A video link: https://youtu.be/USDicKs0vKQ
BVLSI online session 6 B video link: https://youtu.be/upgoE-lkilU
BVLSI online session 6 C video link: https://youtu.be/GuYrSJLD57w
BVLSI online session 6 D video link: https://youtu.be/oOgEtQfoajs
BVLSI online session 5 video link: https://youtu.be/D5f1QsMlNME
BVLSI online session 4 A video link: https://youtu.be/oPSKmARJ2MY
BVLSI online session 4 B video link: https://youtu.be/Y7MnSRiGoc4
BVLSI online session 3 video link: https://youtu.be/v2oyqgvuTDI
BVLSI online session 2 video link: https://youtu.be/xmAuSS3qVJg
BVLSI online session 1 video link: https://youtu.be/624TK-apuUQ